Proposal Title : Hyper - threaded JVM on a FPGA

This project is concerned with researching and implementing a multi-threaded Java Virtual Machine (JVM) that can execute threads concurrently in hardware on a Field Programmable Gate Array (FPGA). A FPGA is a hardware device that has many applications ranging from embedded systems such as Mobile Phones, Signal Processing in Electric Guitars, and PDAs to high performance computing. A standard CPU has a list of instructions that a programmer calls in a specific order to execute the program. With a FPGA the programmer calls just one instruction that creates the program as an electronic circuit on the FPGA. The major difference to note here is that a standard CPU executes single instructions as compared to the FPGA executing the whole program. A JVM is a virtual machine that is able to run Java byte-codes that make up a program. Whatis.com provide a good definition of FPGA [5] and there is a book available for the JVM specification [3]. This JVM will have the ability to execute Java byte-codes directly in hardware as compared to a software JVM that must translate the byte-codes into machine instructions that the CPU can interpret. It will also be able to execute multiple threads in parallel. It will have an increase in speed over a traditional CPU running Java byte-codes due to the byte-codes being directly executed in hardware. Traditional CPUs can only execute one thread (the new Intel XEON can execute two) at a particular moment, they require context switching to switch between different threads. A JVM that can execute multiple threads concurrently in hardware will have a speed advantage over one that can only execute one thread at any particular moment. Kreuzinger et al. [2] have developed a multi-threaded JVM in hardware that is capable of running 4 threads in parallel; their design is a real-time multi-threaded interrupt service system. The aim of this project is to build a JVM which is able to execute lots of threads concurrently in hardware. This project is concerned with a device that can run complex algorithms using multiple threads, instead of having a real-time signal based system.